Describe your registers once.
cloudbust turns a register map into a VHDL register file with a bus endpoint, a self-checking UVVM testbench, C, C++ and Python headers and documentation. For FPGA and ASIC designers who would rather describe registers once than keep them in sync by hand.
Open the editor Try an example
Your register map never leaves your browser. cloudbust runs bust right in the page, and nothing is uploaded.
What you get
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VHDL register file
Registers, fields and a bus endpoint for AXI4-Lite, Avalon-MM, APB, Wishbone, IPbus or SBI, ready to synthesize.
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UVVM testbench
A self-checking testbench that reads and writes every register through the bus.
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C, C++ and Python headers
Register addresses, field masks and positions for the software side, from the same source.
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Documentation
HTML, Markdown and LaTeX, with a register list and the bit layout of every register.
How it works
- Describe. Add registers and fields in the editor, or open a bust JSON file.
- Check. bust checks every change as you make it and points at anything it cannot generate.
- Download. See the documentation and every file update as you edit, then download them as a zip.
Private by design
Register maps are design IP. cloudbust is a static site: bust runs in Pyodide inside your browser, every file it needs comes from this site with a pinned hash, and there is no server that could see your map.
The free cloudbust generates register maps with up to 8 registers. bust itself is open source and has no limit: pip install bust.